We are not only an ASIC IP core vendor, but we also offer RTL design services for LSI and FPGA. In fact, we offer the BETTER design service. HOW? While other design services do design not concerning much about power consumption, gate size, and circuit latency, we improve them in a way no one has ever thought of. Based on our customer's specification and their demands, we design a circuit using our technology called Spinor. Applying the technology, we can archive much lower power, smaller circuit size, and more efficient latency. You will have the dream circuit!!

Our Circuit Design Procedure:
As our customer and we sign up for NDA for each other, we ask our customer for the specification. Shortly after we receive the specification, we figure out the development period based on that. At the same time, we also report our customer the Spinor effect such as the reduction area rate or estimated latency. Seeing our report, our customer can decide signing on our contract. After the actual development, we deliver “the verilog RTL source-code which our customer is able to synthesize on their EDA tool”, “its comprehensive verification test bench”, and “the test vectors”.

Our Service Price:
Both of the license fee and the royalty shall be determined based upon a negotiation between our customer and us. Prior to the negotiation, our estimated Spinor effect on our customer's circuits is also discussed: how much we can reduce the circuit area, how much we can save power consumption, and how much we can shorten the circuit latency.
If predetermined Spinor effect can not be confirmed when our actual development is over, we shall refund any license fee in accordance with our contract.

If you have any question or any request for applying Spinor on your LSI, please feel free to contact us.

Contact Us