The MS1030 is a Fast Fourier Transform (FFT) IP core, which computes the forward FFT and the inverse FFT (IFFT) of 64- or 128-point. The FFT is best used for applications of high speed communications like IEEE 802.11n for ASIC hardware. Mathematec realizes Lower Latency & Area Efficiency using our original LSI circuit design technology, SPINOR.
Additionally, we take the design change request on the IP core to meet the specification of our customer's product.
– Dynamic selection between FFT and IFFT
– 64- or 128-point is selectable
– Configurable order of Output Data
– Continuous real-time operations of FFT frames (See Table 1 below)
– 12-word length input, 12-word length output
– Operation Frequency   80MHz
– Operation throughput   1 point/clock
– Quantization Bit Rate   X12Q8 format of 12-bit fixed point number for both of Input and Output
       Note) The Maximum negative value, 100000000000 should not be used.
       If 100000000000 is inputted, it will be treated as 100000000001 internally.
– Normalization Factor   1/8 for 64-point FFT,   128-1/2 for 128-point FFT
– Sample Rate   1 point/clock for both of Input and Output
– Latency (means total clock cycles from first signal input to first signal output)
    >> 135 clocks for 128-point FFT,   71 clocks for 64-point FFT
– Deliverables
    >> Synthesizable Verilog RTL source code   (Logic Synthesis is confirmed as shown in Figure 2)
    >> Comprehensive Verification test bench and its vectors
Continuous real-time operations are possible except when the points change from 128 to 64. Latencies (clock cycles) to process multiple FFTs are shown as below.

Table 1   Latencies to process multiple FFTs

Figure 1   Block Diagram
The size of this IP core is depended on a Delay Constraint shown as Figure 2, and our customer can choose any one of them.
The latency is only 7 clocks excluding the theoretical limit (128 clocks). This is relatively quite small .

Synopsys's Design Compiler
Version:   A-2007.12-SP2
Library:   ARTISAN TSMC 90nm Gen.

Logic Synthesis Constraints
1. Delay Constraints   9.0ns
2. Maximum Fanout Constraints   non
3. Zero Wireload
4. Operating Condition   Slow

                  Figure 2 Gate Counts & Delay

Note) Figure 2 shows the 2-input-NAND-equivalent gate counts.