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Research and Development of the Area Reduction Technology on LSI & FPGA, and its Commercialization.
Design the fundamental electronic circuits which drastically improve the performance and cost efficiency with the integration of the mathematical science and the technologies. |
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| Company Name |
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Mathematec Corporation |
| Office Location |
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Daisan Shomei Building 8F, 1-18-14, Nihonbashi, Chuo-ku,
Tokyo 103-0027, Japan |
| TEL |
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+81-3-3243-0805 |
| FAX |
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+81-3-3243-0806 |
| E-mail |
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info@mathematec.com |
| Founded |
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April 13, 2000 |
| President & CEO |
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Masao Watari |
| Capital |
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10,000,000 yen |
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